FLASHTIM=1CLK
Flash Accelerator Configuration Register. Controls flash access timing.
| RESERVED | Reserved, user software should not change these bits from the reset value. |
| FLASHTIM | Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved. 0 (1CLK): Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. 1 (2CLK): Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. 2 (3CLK): Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. 3 (4CLK): Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. 4 (5CLK): Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. 5 (6CLK): Flash accesses use 6 CPU clocks. This safe setting will work under any conditions. |
| RESERVED | Reserved. The value read from a reserved bit is not defined. |